Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41075 )
Change subject: soc/amd/picasso: Enable eSPI capability for Picasso ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41075/11/src/soc/amd/picasso/southb... File src/soc/amd/picasso/southbridge.c:
https://review.coreboot.org/c/coreboot/+/41075/11/src/soc/amd/picasso/southb... PS11, Line 210: PICASSO_LPC_IOMUX
I see Mandolin selecting SOC_AMD_COMMON_BLOCK_USE_ESPI. […]
https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src... calls lpc_enable_sio_decode(). On Mnadolin the EC is on eSPI, but the optional debug UART card is on LPC which is why I was worried about breakage due to the eSPI patch train. Not sure if missing LPC pin mux setup is the issue here or if the decode ranges just end up on the wrong bus. The name of PICASSO_LPC_IOMUX suggests that it should do something with the LPC/eMMC muxing; haven't further looked into the issue though.