[coreboot-gerrit] Change in coreboot[master]: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch

[David Jimenez (Code Review)]

David Jimenez has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38947 )

Change subject: mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch
......................................................................

mb/hatch + soc/intel/cannonlake: Enable TetonGlacierMode on hatch

Enabling TetonGlacierMode allows for reconfiguring the PCIe lanes at runtime for hybrid drives.

BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration

Signed-off-by: David Jimenez 
Change-Id: If775b40e6922ac7d111ac00c7c51eec6623ed4df
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
3 files changed, 15 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38947/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index f7cf3cd..f360c10 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -50,6 +50,8 @@
    register "PchUnlockGpioPads" = "1"
    # SD card WP pin confguration
    register "ScsSdCardWpPinEnabled" = "0"
+	# Auto-switch between X4 NVMe and X2 NVMe for hybrid storage support
+	register "TetonGlacierMode" = "1"

# NOTE: if any variant wants to override this value, use the same format
    # as register "common_soc_config.pch_thermal_trip" = "value", instead of
@@ -163,7 +165,7 @@
    register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
    register "usb3_ports[5]" = "USB3_PORT_EMPTY"

-	# Enable Root port 9(x4) for NVMe.
+	# Enable Root port 9(x2) for NVMe.
    register "PcieRpEnable[8]" = "1"
    register "PcieRpLtrEnable[8]" = "1"
    # RP 9 uses CLK SRC 1
@@ -171,6 +173,10 @@
    # ClkReq-to-ClkSrc mapping for CLK SRC 1
    register "PcieClkSrcClkReq[1]" = "1"

+	# Enable Root port 11(x2) for NVMe hybrid storage devices.
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpLtrEnable[10]" = "1"
+
    # PCIe port 14 for M.2 E-key WLAN
    register "PcieRpEnable[13]" = "1"
    register "PcieRpLtrEnable[13]" = "1"
@@ -324,9 +330,9 @@
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9 (X4 NVME)
+		device pci 1d.0 on  end # PCI Express Port 9 (X2 NVME)
    	device pci 1d.1 off end # PCI Express Port 10
-		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.2 on  end # PCI Express Port 11 (x2 NVME)
    	device pci 1d.3 off end # PCI Express Port 12
    	device pci 1d.4 off end # PCI Express port 13
    	device pci 1d.5 on
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index fd37d26..16265d2 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -242,6 +242,9 @@
     * Setting to 0 (default) disables Heci1 and hides the device from OS */
    uint8_t HeciEnabled;

+	// Enables support for Teton Glacier hybrid storage device
+	uint8_t TetonGlacierMode;
+
    /* PL1 Override value in Watts */
    uint32_t tdp_pl1_override;
    /* PL2 Override value in Watts */
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index dc4a2a8..e8ad62f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -374,6 +374,9 @@
 #endif
    params->Device4Enable = config->Device4Enable;

+	/* Teton Glacier hybrid storage support */
+	params->TetonGlacierMode = config->TetonGlacierMode;
+
    /* VrConfig Settings for 5 domains
     * 0 = System Agent, 1 = IA Core, 2 = Ring,
     * 3 = GT unsliced,  4 = GT sliced */