[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: FSP UPD update

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32026 )

Change subject: soc/intel/cannonlake: FSP UPD update
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Patch Set 1:

(2 comments)

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 168: SlpS0WithGbeSupport
Could this be set based on s0ix_enable+PchLanEnable?

The default seems to be enabled except on WHL V0, do we need to account for that in here as well to not try and force it on with WHL V0?

"Default is 0 when paired with WHL V0 stepping CPU and 1 for all other CPUs."

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 169: PchPmSlpS0VmRuntimeControl
What is the downside of enabling these options when config->s0ix_enable is set?