[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Subrata Banik (Code Review)]

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 21:

(1 comment)

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85454/comment/591a0e87_476d721e?usp... :
PS21, Line 387: 	m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING);
> After a good night's sleep, I realize that I want to align with your opinion of not pursuing such an endeavor. There is just so much duplication between all the `soc/intel/[...]lake/*` and, in particular, the `fsp_params.c` that it is tempting to find ways to suppress some of them.
>
> As annoying as it is, if we were to look into ways of improving code sharing in this area, I would stay away from the `fsp_params.c` because User Product Data (UPDs) are outside our control. Common code, even if slightly impacted, would quickly become unmanageable.
>
> If we were to start looking into reducing code duplication, and I am all for it, I would recommend starting with `soc/intel/*/pmc.c`, `soc/intel/*/reset.c`, or `soc/intel/*/retimer.c`.
>
> I am marking this as resolved and abandoning my refactoring changelist (CL).

Thanks for your understanding. I agree that we should focus on optimizing the redundant code pieces you listed in your previous response, rather than optimizing the FSP-UPD-based SoC code.