Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/797c1f95_056407b2 PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC :
Comment about GPP_C = 0xb matches. But the others are different. […]
@Furquan, for GPIO COMM 4 GPP_C0 offset start 0x700 - GPP_C23 offset end 0x880 GPP_F0 offset start 0x880 - GPP_CF3 offset 0xA08
EDS says next is GPP_E_0 at offset start 0xA70 and ends at 0xBF0
There is a hole between GPP_F and GPP_E, actually EDS doesn't capture HVMOS because it doesn't have non-board level configuration GPIO, but to make uniform calculation, i have kept that GPIO which was available in internal document.
Same logic for GPP_SPI0 as well.
I don't understand what you mean by wrong here? can you please help ?