[coreboot-gerrit] Change in coreboot[master]: riscv: add entry assembly file for RAMSTAGE

[Xiang Wang (Code Review)]

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/28384

to look at the new patch set (#3).

Change subject: riscv: add entry assembly file for RAMSTAGE
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riscv: add entry assembly file for RAMSTAGE

RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.

Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/Makefile.inc
A src/arch/riscv/assembly_entry.S
M src/arch/riscv/include/arch/header.ld
3 files changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/3