[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Determine PCIe RP enable mask using device on/of...

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49021 )

Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status
......................................................................

soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status

This change uses the newly added helper function
`pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root
ports that are enabled by the mainboard instead of relying on
PcieRpEnable[] config.

Since pch_lp_rp_groups are used by more than just chip.c, this change
also adds pcie_rp.c that provides a helper function to get the PCIe RP
group table for the PCH.

Signed-off-by: Eric Lai 
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/chip.c
A src/soc/intel/alderlake/include/soc/pcie.h
A src/soc/intel/alderlake/pcie_rp.c
4 files changed, 43 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/49021/1

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index d962b75..f31cf98 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -25,6 +25,7 @@
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
+romstage-y += pcie_rp.c
 romstage-y += reset.c

ramstage-y += acpi.c
@@ -38,6 +39,7 @@
 ramstage-y += lockdown.c
 ramstage-y += me.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += smmrelocate.c
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 794c3ba..67cfe32 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -13,15 +13,10 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>

-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {
@@ -149,7 +144,7 @@
    soc_fill_gpio_pm_configuration();

/* Swap enabled PCI ports in device tree if needed. */
-	pcie_rp_update_devicetree(pch_lp_rp_groups);
+	pcie_rp_update_devicetree(get_pch_pcie_rp_table());
 }

static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/alderlake/include/soc/pcie.h b/src/soc/intel/alderlake/include/soc/pcie.h
new file mode 100644
index 0000000..effc8e2
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/pcie.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_ALDERLAKE_PCIE_H__
+#define __SOC_ALDERLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void);
+const struct pcie_rp_group *get_cpu_pcie_rp_table(void);
+
+#endif /* __SOC_ALDERLAKE_PCIE_H__ */
+
diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
new file mode 100644
index 0000000..de7e015
--- /dev/null
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+static const struct pcie_rp_group pch_lp_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 4 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_pch_pcie_rp_table(void)
+{
+	return pch_lp_rp_groups;
+}
+
+/* TODO check how to determine CPU PCIE port */
+static const struct pcie_rp_group cpu_rp_groups[] = {
+	{ .slot = SA_DEV_SLOT_CPU_PCIE, .count = 1 },
+	{ 0 }
+};
+
+const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
+{
+	return cpu_rp_groups;
+}