Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33189 )
Change subject: soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33189/1/src/soc/intel/icelake/graphics.c File src/soc/intel/icelake/graphics.c:
https://review.coreboot.org/#/c/33189/1/src/soc/intel/icelake/graphics.c@48 PS1, Line 48: DDI_A_4_LANES
Those registers are applicable for ICL as well. And also how do you know that we haven't check if removing those code not giving any problem ?
Because I currently assume that you would have removed it, then. As long as you can't provide any documentation that ICL knows this bifurcation setting, I'll assume that it doesn't.
I guess comments are enough to understand the problem without those GT programming in coreboot
/*
- Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
- This will allow the kernel to use 4-lane eDP links properly
- if the VBIOS or GOP driver do not execute.
*/
It won't cause any CB issue rather kerner display won't come over eDP when we skip executing GOP/VBIOS, which is typically happening during normal mode.
More details here: https://review.coreboot.org/13690
Don't have to tell me what this code does / tries to do, I'm rather an expert for this part of Intel silicon. And showing reviews for SKL doesn't tell anything about ICL anyway.