Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36410 )
Change subject: soc/intel/common: move common memmap functionality from skl,icl,cnl,apl ......................................................................
soc/intel/common: move common memmap functionality from skl,icl,cnl,apl
This moves common memmap functionality from skl,icl,cnl,apl to the common tree.
Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac Signed-off-by: Michael Niewöhner foss@mniewoehner.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/apollolake/memmap.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/systemagent/Makefile.inc A src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/icelake/memmap.c M src/soc/intel/skylake/memmap.c 6 files changed, 51 insertions(+), 104 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 7b60270..f828024 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -15,14 +15,8 @@ * GNU General Public License for more details. */
-#include <arch/romstage.h> -#include <assert.h> #include <cbmem.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/smm.h> -#include <device/pci.h> #include <soc/systemagent.h> -#include <soc/pci_devs.h>
#include "chip.h"
@@ -42,28 +36,3 @@
return tolum; } - -void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - /* cbmem_top() needs to be at least 16 MiB aligned */ - assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, - MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 80aa97d..475b8c7 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -31,12 +31,6 @@
#include "chip.h"
-void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == @@ -261,21 +255,3 @@
return (void *)(uintptr_t)ebda_cfg.tolum_base; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/common/block/systemagent/Makefile.inc b/src/soc/intel/common/block/systemagent/Makefile.inc index 0c29636..7e49ec7 100644 --- a/src/soc/intel/common/block/systemagent/Makefile.inc +++ b/src/soc/intel/common/block/systemagent/Makefile.inc @@ -3,3 +3,6 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent_early.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += systemagent.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SA) += memmap.c diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c new file mode 100644 index 0000000..ea22aa6 --- /dev/null +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <intelblocks/systemagent.h> +#include <stdlib.h> + +void smm_region(uintptr_t *start, size_t *size) +{ + *start = sa_get_tseg_base(); + *size = sa_get_tseg_size(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + /* Cache the TSEG region */ + postcar_enable_tseg_cache(pcf); +} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 00f45cf..f17f255 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -29,12 +29,6 @@ #include <soc/systemagent.h> #include <stdlib.h>
-void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - /* Calculate ME Stolen size */ static size_t get_imr_size(void) { @@ -240,21 +234,3 @@
return (void *)(uintptr_t)ebda_cfg.tolum_base; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -} diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index c6ccd71..3aea1c3 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -32,12 +32,6 @@
#include "chip.h"
-void smm_region(uintptr_t *start, size_t *size) -{ - *start = sa_get_tseg_base(); - *size = sa_get_tseg_size(); -} - static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == @@ -262,22 +256,3 @@
return (void *)(uintptr_t)ebda_cfg.tolum_base; } - -void fill_postcar_frame(struct postcar_frame *pcf) -{ - uintptr_t top_of_ram; - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t) cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); -}