Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44382 )
Change subject: soc/ti/am335x: Enable MMU in bootblock ......................................................................
soc/ti/am335x: Enable MMU in bootblock
Enables the MMU primarily to allow the unaligned word reads that the FMAP code requires. Without enabling this, the chip gets data access exceptions.
Enabling the MMU also gives some advantages in allowing the icache and dcache to be enabled, so is probably worth doing regardless.
Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf Signed-off-by: Sam Lewis sam.vr.lewis@gmail.com --- M src/soc/ti/am335x/bootblock.c M src/soc/ti/am335x/bootblock_media.c M src/soc/ti/am335x/memlayout.ld 3 files changed, 22 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44382/1
diff --git a/src/soc/ti/am335x/bootblock.c b/src/soc/ti/am335x/bootblock.c index 985e1a1..11bc459 100644 --- a/src/soc/ti/am335x/bootblock.c +++ b/src/soc/ti/am335x/bootblock.c @@ -4,13 +4,25 @@
#include <arch/cache.h> #include <bootblock_common.h> +#include <symbols.h> + +#define SRAM_START ((uintptr_t)_sram / MiB) +#define SRAM_END (DIV_ROUND_UP((uintptr_t)_esram, MiB)) + +#define DRAM_START ((uintptr_t)_dram / MiB) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
void bootblock_soc_init(void) { - uint32_t sctlr; + mmu_init();
- /* enable dcache */ - sctlr = read_sctlr(); - sctlr |= SCTLR_C; - write_sctlr(sctlr); + /* Map everything strongly ordered by default */ + mmu_config_range(0, 4096, DCACHE_OFF); + + mmu_config_range(SRAM_START, SRAM_END - SRAM_START, + DCACHE_WRITEBACK); + + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + + dcache_mmu_enable(); } diff --git a/src/soc/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c index 1c65c38..b7e49a6 100644 --- a/src/soc/ti/am335x/bootblock_media.c +++ b/src/soc/ti/am335x/bootblock_media.c @@ -3,7 +3,6 @@ #include <boot_device.h> #include <symbols.h>
-/* FIXME: No idea how big the internal SRAM actually is. */ static const struct mem_region_device boot_dev = MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE);
diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 991e401..16770a5 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -8,17 +8,16 @@ { SRAM_START(0x402f0400) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) - FMAP_CACHE(0x4030b400, 2K) + FMAP_CACHE(0x402f0400+20K, 2K) + TTB(0x402F8000, 16K) + ROMSTAGE(0x402F8000+16K, 40K) + STACK(0x4030be00, 4K) SRAM_END(0x40310000) DRAM_START(0x80000000)
RAMSTAGE(0x80200000, 192K)
- /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x81000000, 16K) - #ifdef OMAP_HEADER .header : { *(.header); @@ -26,6 +25,6 @@
/DISCARD/ : { *(*) - } +} #endif }