Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36774 )
Change subject: cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK ......................................................................
cpu/intel/slot_1: Move to C_ENVIRONMENT_BOOTBLOCK
Console is not yet enabled in bootblock. This will be done in a different CL.
Change-Id: Ic751d42a1969fb79fb50366f766d8796846a0bc4 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/slot_1/Makefile.inc M src/northbridge/intel/i440bx/Kconfig M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82371eb/Makefile.inc M src/southbridge/intel/i82371eb/bootblock.c 6 files changed, 18 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36774/1
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 3d0522a..05676b2 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -26,6 +26,7 @@ select NO_SMM select NO_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select C_ENVIRONMENT_BOOTBLOCK
config DCACHE_RAM_BASE hex @@ -35,4 +36,12 @@ hex default 0x02000
+config DCACHE_BSP_STACK_SIZE + hex + default 0x1000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x2000 + endif diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 599a5d0..bc9cda0 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -26,6 +26,8 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode
-cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S +bootblock-y += ../car/p3/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 45cdd9c..01154da 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -18,6 +18,7 @@ select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select UDELAY_IO + select NO_BOOTBLOCK_CONSOLE
config SDRAMPWR_4DIMM bool diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 6552099..31bc3cc 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -3,8 +3,3 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS bool - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 131010f..390fd97 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -16,6 +16,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
+bootblock-y += bootblock.c + ramstage-y += i82371eb.c ramstage-y += isa.c ramstage-y += ide.c diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 2b8cd1f..0eb2e4f 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <device/pci_type.h> +#include <cpu/intel/car/bootblock.h> #include "i82371eb.h"
#define PCI_ID(VENDOR_ID, DEVICE_ID) \ @@ -34,7 +35,8 @@ return PCI_DEV_INVALID; }
-static void bootblock_southbridge_init(void) +/* TODO: Does not need to happen before console init */ +void bootblock_early_southbridge_init(void) { u16 reg16; pci_devfn_t dev;