Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 9:
(5 comments)
Looks good overall, just some open questions. Also, does this RC have a date on it by any chance?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/lpc.c:
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 499: } This was run on LPT-LP before, right? Can we be sure it's not needed?
Nvm, I found a table that says 24a4/8 were removed.
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 318: Set *Clear* again?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 360: RCBA32_OR(0x3318, 0x0dcf0020); BIOS spec says something about bit 5 here. It should reflect the value you want on GPIO 8 if it's in native mode (it is on the B85M Pro4, AFAICS). Do we know what it does?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 388: RCBA32(0x2b2c) = 0x00008813; BIOS Spec uses this value for LPT-LP, but 0 along with the other values in this block in a sequence for "MB Only"... any clue?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 392: 4 That's bit 18 set, right? Spec also suggests this value but then the same SATA port story for bits 18+20, 24+26 as is already implemented for LP. Did you test SATA ports 0..3 by any chance?