Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 114 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47208/1
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8cc6a87..6830051 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -114,6 +114,17 @@
RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
+ RCBA32(0x2088) = 0x00109000; + + RCBA32_OR(0x20ac, 1 << 30); + + if (!pch_is_lp()) { + RCBA32_AND_OR(0x2340, ~(0xff << 0), 0x1b << 0); + RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16); + + RCBA32(0x2324) = 0x00854c74; + } + wake_from_s3 = southbridge_detect_s3_resume();
elog_boot_notify(wake_from_s3); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 64515e9..a046099 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -289,10 +289,111 @@ RCBA16(0x3f02) = reg16; }
+static void configure_dmi_pm(struct device *dev) +{ + struct device *const pcie_dev = pcidev_on_root(0x1c, 0); + + /* Additional PCH DMI programming steps */ + + /* EL0 */ + u32 reg32 = 3 << 12; + + /* EL1 */ + if (pcie_dev && !(pci_read_config8(pcie_dev, 0xf5) & 1 << 0)) + reg32 |= 2 << 15; + else + reg32 |= 4 << 15; + + RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32); + + RCBA32_AND_OR(0x2348, ~0xf, 0); + + /* Clear prior to enabling DMI ASPM */ + RCBA32_AND_OR(0x2304, ~(1 << 10), 0); + + RCBA32_OR(0x21a4, 3 << 10); + + RCBA16(0x21a8) |= 3 << 0; + + /* Set again after enabling DMI ASPM */ + RCBA32_AND_OR(0x2304, ~(1 << 10), 0); +} + /* LynxPoint PCH Power Management init */ static void lpt_pm_init(struct device *dev) { + struct device *const pcie_dev = pcidev_on_root(0x1c, 0); + printk(BIOS_DEBUG, "LynxPoint PM init\n"); + + /* Configure additional PM */ + + pci_write_config8(dev, 0xa9, 0x46); + + pci_or_config32(dev, PMIR, PMIR_CF9LOCK); + + /* Step 3 is skipped */ + + /* Program DMI Hardware Width Control (thermal throttling) */ + u32 reg32 = 0; + reg32 |= 1 << 0; /* DMI Thermal Sensor Autonomous Width Enable */ + reg32 |= 0 << 4; /* Thermal Sensor 0 Target Width */ + reg32 |= 1 << 6; /* Thermal Sensor 1 Target Width */ + reg32 |= 1 << 8; /* Thermal Sensor 2 Target Width */ + reg32 |= 2 << 10; /* Thermal Sensor 3 Target Width */ + RCBA32(0x2238) = reg32; + + RCBA32_OR(0x232c, 1 << 0); + RCBA32_OR(0x1100, 3 << 13); /* Assume trunk clock gating is to be enabled */ + + RCBA32(0x2304) = 0xc07b8400; /* DMI misc control */ + + RCBA32_OR(0x2314, 1 << 23 | 1 << 5); + + if (pcie_dev) + pci_update_config8(pcie_dev, 0xf5, ~0xf, 0x5); + + RCBA32_OR(0x2320, 1 << 1); + + RCBA32(0x3314) = 0x000007bf; + + RCBA32_OR(0x3318, 0x0dcf0020); + + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3340) = 0x020ddbff; + + RCBA32_OR(0x3344, 1 << 0); + + RCBA32(0x3368) = 0x00041000; + RCBA32(0x3378) = 0x3f8ddbff; + RCBA32(0x337c) = 0x000001e1; + RCBA32(0x3388) = 0x00001000; + RCBA32(0x33a0) = 0x00000800; + RCBA32(0x33ac) = 0x00001000; + RCBA32(0x33b0) = 0x00001000; + RCBA32(0x33c0) = 0x00011900; + RCBA32(0x33d0) = 0x06000802; + RCBA32(0x3a28) = 0x01010000; + RCBA32(0x3a2c) = 0x01010404; + + /* Step 31 */ + RCBA32_OR(0x33a4, 1 << 0); + + /* DMI power optimizer */ + RCBA32_OR(0x33d4, 1 << 27); + RCBA32_OR(0x33c8, 1 << 27); + RCBA32(0x2b14) = 0x1e0a0317; + RCBA32(0x2b24) = 0x4000000b; + RCBA32(0x2b28) = 0x00000002; + RCBA32(0x2b2c) = 0x00008813; + + /* Step 55 */ + RCBA32(0x3a80) = 0x01040000; + RCBA32(0x3a84) = 0x01041001; + RCBA32(0x3a88) = 0x00000001; + RCBA32(0x33d4) = 0xc80bc000; + + configure_dmi_pm(dev); }
/* LynxPoint LP PCH Power Management init */ @@ -485,19 +586,6 @@ pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); }
-static void pch_fixups(struct device *dev) -{ - /* Indicate DRAM init done for MRC S3 to know it can resume */ - pci_or_config8(dev, GEN_PMCON_2, 1 << 7); - - /* - * Enable DMI ASPM in the PCH - */ - RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); - RCBA32_OR(0x21a8, 0x3); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -545,7 +633,8 @@
pch_set_acpi_mode();
- pch_fixups(dev); + /* Indicate DRAM init done for MRC S3 to know it can resume */ + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); }
static void pch_lpc_add_mmio_resources(struct device *dev)
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 4:
I've started to compare this to the spec, but... do we know that the blob doesn't do this already?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 4:
Patch Set 4:
I've started to compare this to the spec, but... do we know that the blob doesn't do this already?
Which blob? The MRC.bin, which I'm going to get rid of? ;)
BTW, the MRC version in MRC.bin is 1.6.0 build 0, and I assume the rest of RC (Reference Code) is also version 1.6.0 or similar. I know MRC version 1.9.0 comes with version 1.9.1 of the PCH RC. So, even if MRC did something, it may not be up-to-date.
I've implemented most of this after checking register dumps after booting with MRC. Without this patch, nearly all of the registers don't have the expected values, which means MRC doesn't do it. I think a few registers already had the correct values, but I don't know if that's their reset default value or if MRC actually programmed them, but since MRC is going to become optional, I decided to program all of them anyway. There's no harm in writing a few registers twice, and simplifies the future when MRC's reign of terror is eventually brought to an end. *laughs maniacally*
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 4:
I've implemented most of this after checking register dumps after booting with MRC. Without this patch, nearly all of the registers don't have the expected values, which means MRC doesn't do it.
If you checked, please put that in the commit message. In the long run it may be more interesting what the code is based on, but for review and regression assessment, it's crucial to know what changes.
I currently stare too much at code already during the day, but I'll try to find more time for review soon.
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47208
to look at the new patch set (#5).
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 114 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47208/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 5:
Patch Set 4:
I've implemented most of this after checking register dumps after booting with MRC. Without this patch, nearly all of the registers don't have the expected values, which means MRC doesn't do it.
If you checked, please put that in the commit message. In the long run it may be more interesting what the code is based on, but for review and regression assessment, it's crucial to know what changes.
I currently stare too much at code already during the day, but I'll try to find more time for review soon.
Updated the commit message with a sentence.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 9:
(5 comments)
Looks good overall, just some open questions. Also, does this RC have a date on it by any chance?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/lpc.c:
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 499: } This was run on LPT-LP before, right? Can we be sure it's not needed?
Nvm, I found a table that says 24a4/8 were removed.
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 318: Set *Clear* again?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 360: RCBA32_OR(0x3318, 0x0dcf0020); BIOS spec says something about bit 5 here. It should reflect the value you want on GPIO 8 if it's in native mode (it is on the B85M Pro4, AFAICS). Do we know what it does?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 388: RCBA32(0x2b2c) = 0x00008813; BIOS Spec uses this value for LPT-LP, but 0 along with the other values in this block in a sequence for "MB Only"... any clue?
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 392: 4 That's bit 18 set, right? Spec also suggests this value but then the same SATA port story for bits 18+20, 24+26 as is already implemented for LP. Did you test SATA ports 0..3 by any chance?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/lpc.c:
https://review.coreboot.org/c/coreboot/+/47208/9/src/southbridge/intel/lynxp... PS9, Line 360: RCBA32_OR(0x3318, 0x0dcf0020);
BIOS spec says something about bit 5 here. It should reflect the value you […]
GPIO8 is used for overclocking, c.f. Haswell BWG
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Tristan Corrick, Paul Menzel, Arthur Heymans, Michael Niewöhner, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47208
to look at the new patch set (#10).
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 122 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47208/10
Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 9:
(5 comments)
File src/southbridge/intel/lynxpoint/lpc.c:
https://review.coreboot.org/c/coreboot/+/47208/comment/c26bdafa_3bca7775 PS9, Line 499: }
This was run on LPT-LP before, right? Can we be sure it's not needed? […]
DMI doesn't exist as such on LPT-LP. Reference code only programs these registers for LPT-H, and the WPT-LP docs I have don't mention the 21a4/a8 registers. About 0x2304, the WPT-LP BIOS spec says nothing (only that it was removed from the programming steps), and the EDS says the following:
BIOS must program this field to F88400h.
https://review.coreboot.org/c/coreboot/+/47208/comment/15ac042a_070a68f8 PS9, Line 318: Set
*Clear* again?
No, the comment is right. The code was wrong.
https://review.coreboot.org/c/coreboot/+/47208/comment/06cb0c33_2961f364 PS9, Line 360: RCBA32_OR(0x3318, 0x0dcf0020);
GPIO8 is used for overclocking, c.f. […]
Bit 5 needs to be preserved. I can't find any mentions about GPIO8 on the Haswell BWG, maybe I misremembered.
https://review.coreboot.org/c/coreboot/+/47208/comment/3ebf86d9_1828efd6 PS9, Line 388: RCBA32(0x2b2c) = 0x00008813;
BIOS Spec uses this value for LPT-LP, but 0 along with the other values in […]
Reference code also uses this value on LPT-LP, but writes it earlier and to a different register. This sequence, as the comment says, is part of the DMI power optimizer, but code does nothing special w.r.t. "MB only".
https://review.coreboot.org/c/coreboot/+/47208/comment/95b382ab_ec3e7d07 PS9, Line 392: 4
That's bit 18 set, right? Spec also suggests this value but then the same […]
I've revised this as per reference code, but I agree it makes no sense.
Attention is currently required from: Nico Huber. Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Tristan Corrick, Paul Menzel, Arthur Heymans, Michael Niewöhner, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47208
to look at the new patch set (#13).
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 122 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47208/13
Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
Patch Set 15: Code-Review+2
(1 comment)
Patchset:
PS15: Thanks for the patience.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47208 )
Change subject: sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1 ......................................................................
sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 122 insertions(+), 15 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 75aaf67..2d0a53d 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -113,6 +113,17 @@
RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
+ RCBA32(0x2088) = 0x00109000; + + RCBA32_OR(0x20ac, 1 << 30); + + if (!pch_is_lp()) { + RCBA32_AND_OR(0x2340, ~(0xff << 0), 0x1b << 0); + RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16); + + RCBA32(0x2324) = 0x00854c74; + } + wake_from_s3 = southbridge_detect_s3_resume();
elog_boot_notify(wake_from_s3); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a37f1a2..cf80e64 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -286,10 +286,118 @@ RCBA16(0x3f02) = reg16; }
+static void configure_dmi_pm(struct device *dev) +{ + struct device *const pcie_dev = pcidev_on_root(0x1c, 0); + + /* Additional PCH DMI programming steps */ + + /* EL0 */ + u32 reg32 = 3 << 12; + + /* EL1 */ + if (pcie_dev && !(pci_read_config8(pcie_dev, 0xf5) & 1 << 0)) + reg32 |= 2 << 15; + else + reg32 |= 4 << 15; + + RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32); + + RCBA32_AND_OR(0x2348, ~0xf, 0); + + /* Clear prior to enabling DMI ASPM */ + RCBA32_AND_OR(0x2304, ~(1 << 10), 0); + + RCBA32_OR(0x21a4, 3 << 10); + + RCBA16(0x21a8) |= 3 << 0; + + /* Set again after enabling DMI ASPM */ + RCBA32_OR(0x2304, 1 << 10); +} + /* LynxPoint PCH Power Management init */ static void lpt_pm_init(struct device *dev) { - printk(BIOS_DEBUG, "LynxPoint PM init\n"); + struct southbridge_intel_lynxpoint_config *config = dev->chip_info; + + struct device *const pcie_dev = pcidev_on_root(0x1c, 0); + + printk(BIOS_DEBUG, "LynxPoint H PM init\n"); + + /* Configure additional PM */ + pci_write_config8(dev, 0xa9, 0x46); + + pci_or_config32(dev, PMIR, PMIR_CF9LOCK); + + /* Step 3 is skipped */ + + /* Program DMI Hardware Width Control (thermal throttling) */ + u32 reg32 = 0; + reg32 |= 1 << 0; /* DMI Thermal Sensor Autonomous Width Enable */ + reg32 |= 0 << 4; /* Thermal Sensor 0 Target Width */ + reg32 |= 1 << 6; /* Thermal Sensor 1 Target Width */ + reg32 |= 1 << 8; /* Thermal Sensor 2 Target Width */ + reg32 |= 2 << 10; /* Thermal Sensor 3 Target Width */ + RCBA32(0x2238) = reg32; + + RCBA32_OR(0x232c, 1 << 0); + RCBA32_OR(0x1100, 3 << 13); /* Assume trunk clock gating is to be enabled */ + + RCBA32(0x2304) = 0xc07b8400; /* DMI misc control */ + + RCBA32_OR(0x2314, 1 << 23 | 1 << 5); + + if (pcie_dev) + pci_update_config8(pcie_dev, 0xf5, ~0xf, 0x5); + + RCBA32_OR(0x2320, 1 << 1); + + RCBA32(0x3314) = 0x000007bf; + + /* NOTE: Preserve bit 5 */ + RCBA32_OR(0x3318, 0x0dcf0000); + + RCBA32(0x3324) = 0x04000000; + RCBA32(0x3340) = 0x020ddbff; + + RCBA32_OR(0x3344, 1 << 0); + + RCBA32(0x3368) = 0x00041000; + RCBA32(0x3378) = 0x3f8ddbff; + RCBA32(0x337c) = 0x000001e1; + RCBA32(0x3388) = 0x00001000; + RCBA32(0x33a0) = 0x00000800; + RCBA32(0x33ac) = 0x00001000; + RCBA32(0x33b0) = 0x00001000; + RCBA32(0x33c0) = 0x00011900; + RCBA32(0x33d0) = 0x06000802; + RCBA32(0x3a28) = 0x01010000; + RCBA32(0x3a2c) = 0x01010404; + + RCBA32_OR(0x33a4, 1 << 0); + + /* DMI power optimizer */ + RCBA32_OR(0x33d4, 1 << 27); + RCBA32_OR(0x33c8, 1 << 27); + RCBA32(0x2b14) = 0x1e0a0317; + RCBA32(0x2b24) = 0x4000000b; + RCBA32(0x2b28) = 0x00000002; + RCBA32(0x2b2c) = 0x00008813; + + RCBA32(0x3a80) = 0x01040000; + reg32 = 0x01041001; + /* Port 1 and 0 disabled */ + if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) + reg32 |= (1 << 20) | (1 << 18); + /* Port 3 and 2 disabled */ + if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) + reg32 |= (1 << 24) | (1 << 26); + RCBA32(0x3a84) = reg32; + RCBA32(0x3a88) = 0x00000001; + RCBA32(0x33d4) = 0xc80bc000; + + configure_dmi_pm(dev); }
/* LynxPoint LP PCH Power Management init */ @@ -475,19 +583,6 @@ apm_control(APM_CNT_ACPI_DISABLE); }
-static void pch_fixups(struct device *dev) -{ - /* Indicate DRAM init done for MRC S3 to know it can resume */ - pci_or_config8(dev, GEN_PMCON_2, 1 << 7); - - /* - * Enable DMI ASPM in the PCH - */ - RCBA32_AND_OR(0x2304, ~(1 << 10), 0); - RCBA32_OR(0x21a4, (1 << 11) | (1 << 10)); - RCBA32_OR(0x21a8, 0x3); -} - static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: %s\n", __func__); @@ -528,7 +623,8 @@
pch_set_acpi_mode();
- pch_fixups(dev); + /* Indicate DRAM init done for MRC S3 to know it can resume */ + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); }
static void pch_lpc_add_mmio_resources(struct device *dev)
-
Angel Pons (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)