Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85010?usp=email )
Change subject: mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8 ......................................................................
mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements.
BUG=b:377400590 TEST=Tested on Drawman with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 BRANCH=firmware-dedede-13606.B
Change-Id: Ib9a393dbc23e80633bf01ccdab75286e3c636c8f Signed-off-by: Robert Chen robert.chen@quanta.corp-partner.google.com --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 5 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/85010/1
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 26c5729..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 26c572974bcf7255930b0e9a51da3144ed0104b5 +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index 45f1b75..fe7040a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 45f1b757402f9a0ae8a4e021a8f5745318515308 +Subproject commit fe7040a278642dc3d28e20eb7e7866cb6e2ac2ac diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 129f82f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 129f82f7429c29976b15d6837d2f573cc6a02c26 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index a252198..9d52d27 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit a252198ec6544e13904cfe831cec3e784aaa715d +Subproject commit 9d52d272e1b883d5560d84303526972a220cc678 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 67c9262..6c745d9 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -7,6 +7,9 @@ end chip soc/intel/jasperlake
+ # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera