Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31477 )
Change subject: riscv: workaround selfboot putting the coreboot table into prog_entry_arg
......................................................................
Patch Set 8:
Thanks. Can you add this to the commit message?
On RISC-V the argument to a payload is always the hartid and a
pointer to a FDT.
selfboot sets the coreboot tables as an argument, work around this
here.
Thank you! Done
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