[coreboot-gerrit] Patch merged into coreboot/master: 430bf0d baytrail: Add support for LPSS and SCC devices in ACPI mode

the following patch was just integrated into master:
commit 430bf0d8a96bf9bb3c343c5cf63c6ae8482c532c
Author: Duncan Laurie 
Date:   Tue Dec 10 14:37:42 2013 -0800

baytrail: Add support for LPSS and SCC devices in ACPI mode

This adds the option to put LPSS and SCC devices into ACPI mode
    by saving their BAR0 and BAR1 base addresses in a new device
    NVS structure that is placed at offset 0x1000 within the global
    NVS table.

The Chrome NVS strcture is padded out to 0xf00 bytes so there
    is a clean offset to work with as it will need to be used by
    depthcharge to know what addresses devices live at.

A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and
    the EMMC 4.5 IRQ is changed to 44.

New ACPI code is provided to instantiate the LPSS and SCC devices
    with the magic HID values from Intel so the kernel drivers can
    locate and use them.

The default is still for devices to be in PCI mode so this does
    not have any real effect without it being enabled in the mainboard
    devicetree.

Note: this needs the updated IASL compiler which is in the CQ now
    because it uses the FixedDMA() ACPI operator.

BUG=chrome-os-partner:23505,chrome-os-partner:24380
    CQ-DEPEND=CL:179459,CL:179364
    BRANCH=none
    TEST=manual tests on rambi device:

1) build and boot with devices still in PCI mode and ensure that
    nothing is changed

2) enable lpss_acpi_mode and see I2C devices detected by the kernel
    in ACPI mode.  Note that by itself this breaks trackpad probing so
    that will need to be implemented before it is enabled.

3) enable scc_acpi_mode and see EMMC and SDCard devices detected by
    the kernel in ACPI mode.  Note that this breaks depthcharge use of
    the EMMC because it is not longer discoverable as a PCI device.

Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73
    Signed-off-by: Duncan Laurie 
    Reviewed-on: https://chromium-review.googlesource.com/179481
    Reviewed-by: Aaron Durbin 
    Signed-off-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/5004
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki

See http://review.coreboot.org/5004 for details.

-gerrit