Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67753 )
Change subject: Revert "mb/google/brya/var/kinox: Update the DPTF parameters and fan table" ......................................................................
Revert "mb/google/brya/var/kinox: Update the DPTF parameters and fan table"
This reverts commit 7afa1bae2b8cf941ad9e8af38465030f9d1168a6.
Reason for revert: The fan table AC8/AC9 makes DPTF can not read thermal sensor temperature.
BUG=b:244657172 TEST=Build and boot to Chrome OS. Make sure DPTF can read temperature.
Signed-off-by: Dtrain Hsu dtrain_hsu@compal.corp-partner.google.com Change-Id: I3b5a898956345ae07dfc1f6dc89a87668bdb9db1 --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 66 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/67753/1
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 8356320..a874b1d 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -69,8 +69,6 @@ .tdp_pl1_override = 30, }"
- register "tcc_offset" = "6" - device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -84,63 +82,68 @@ ## Active Policy register "policies.active" = "{ [0] = { - .target = DPTF_TEMP_SENSOR_0, + .target = DPTF_CPU, .thresholds = { - TEMP_PCT(90, 97), - TEMP_PCT(60, 80), - TEMP_PCT(55, 70), - TEMP_PCT(50, 64), - TEMP_PCT(45, 54), - TEMP_PCT(42, 47), - TEMP_PCT(38, 43), + TEMP_PCT(80, 97), + TEMP_PCT(65, 93), + TEMP_PCT(58, 86), + TEMP_PCT(50, 80), + TEMP_PCT(45, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), TEMP_PCT(35, 40), - TEMP_PCT(33, 36), - TEMP_PCT(30, 32), } }, [1] = { - .target = DPTF_TEMP_SENSOR_1, + .target = DPTF_TEMP_SENSOR_0, .thresholds = { - TEMP_PCT(90, 97), - TEMP_PCT(60, 80), - TEMP_PCT(55, 70), - TEMP_PCT(50, 64), - TEMP_PCT(45, 54), - TEMP_PCT(42, 47), - TEMP_PCT(38, 43), + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), TEMP_PCT(35, 40), - TEMP_PCT(33, 36), - TEMP_PCT(30, 32), } }, [2] = { - .target = DPTF_TEMP_SENSOR_2, + .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(90, 97), - TEMP_PCT(60, 80), - TEMP_PCT(55, 70), - TEMP_PCT(50, 64), - TEMP_PCT(45, 54), - TEMP_PCT(42, 47), - TEMP_PCT(38, 43), + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), TEMP_PCT(35, 40), - TEMP_PCT(33, 36), - TEMP_PCT(30, 32), } }, [3] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), + TEMP_PCT(35, 40), + } + }, + [4] = { .target = DPTF_TEMP_SENSOR_3, .thresholds = { - TEMP_PCT(90, 97), - TEMP_PCT(60, 80), - TEMP_PCT(55, 70), - TEMP_PCT(50, 64), - TEMP_PCT(45, 54), - TEMP_PCT(42, 47), - TEMP_PCT(38, 43), + TEMP_PCT(75, 97), + TEMP_PCT(70, 93), + TEMP_PCT(60, 86), + TEMP_PCT(52, 80), + TEMP_PCT(47, 64), + TEMP_PCT(43, 52), + TEMP_PCT(40, 47), TEMP_PCT(35, 40), - TEMP_PCT(33, 36), - TEMP_PCT(30, 32), } } }" @@ -157,10 +160,10 @@ ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 97, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 97, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 97, SHUTDOWN), - [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 97, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 93, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 93, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 93, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 93, SHUTDOWN), }"
register "controls.power_limits" = "{