Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86874?usp=email )
Change subject: soc/amd/common/psp_verstage: Remove arch/io.h ......................................................................
soc/amd/common/psp_verstage: Remove arch/io.h
The arch include files are overshadowed by PSP verstage include files. The reason is that psp_verstage implements its own set of inb() and outb() functions, which use a runtime configurable IO base address instead of a built time constant.
But this works at the moment only because of the order in which the include files are added. Since that is very error prone, this patch introduces another solution to the problem.
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: I16fa4a4cb5168024aaef30119e9aa8a34dbaacbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/86874 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/device/Kconfig M src/include/arch-generic/io.h M src/lib/Makefile.mk A src/lib/io.c M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/emulation/qemu-aarch64/mmio.c M src/soc/amd/common/psp_verstage/fch.c D src/soc/amd/common/psp_verstage/include/arch/io.h 8 files changed, 19 insertions(+), 43 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/device/Kconfig b/src/device/Kconfig index bcff6fd..af3fe80 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -558,12 +558,6 @@ bool default n
-config PCI_IOBASE - hex - help - The memory address of a memory-mapped translator that lets the - CPU communicate with peripheral devices over PCI I/O space. - if PCI
config DOMAIN_RESOURCE_32BIT_LIMIT diff --git a/src/include/arch-generic/io.h b/src/include/arch-generic/io.h index 5874fc8..30f331e 100644 --- a/src/include/arch-generic/io.h +++ b/src/include/arch-generic/io.h @@ -19,7 +19,12 @@ #include <endian.h> #include <arch/mmio.h>
-#define __io(a) (void *)(uintptr_t)(CONFIG_PCI_IOBASE + a) +/* + * The memory address of a memory-mapped translator that lets the + * CPU communicate with peripheral devices over PCI I/O space. + */ +extern uintptr_t io_port_mmio_base; +#define __io(a) (void *)(io_port_mmio_base + a)
static inline void outb(uint8_t value, uint16_t port) { diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk index 84b982d..e0bec03 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk @@ -291,6 +291,10 @@ postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c postcar-$(CONFIG_GENERIC_UDELAY) += timer.c
+all-$(CONFIG_ARCH_ARM) += io.c +all-$(CONFIG_ARCH_ARM64) += io.c +all-$(CONFIG_ARCH_RISCV) += io.c + # Use program.ld for all the platforms which use C fo the bootblock. bootblock-y += program.ld
diff --git a/src/lib/io.c b/src/lib/io.c new file mode 100644 index 0000000..a5808d6 --- /dev/null +++ b/src/lib/io.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> + +uintptr_t __weak io_port_mmio_base = 0; diff --git a/src/mainboard/emulation/qemu-aarch64/Kconfig b/src/mainboard/emulation/qemu-aarch64/Kconfig index 42f9110..c0f579e 100644 --- a/src/mainboard/emulation/qemu-aarch64/Kconfig +++ b/src/mainboard/emulation/qemu-aarch64/Kconfig @@ -30,9 +30,6 @@ config ECAM_MMCONF_BUS_NUMBER default 256
-config PCI_IOBASE - default 0x3eff0000 - config MEMLAYOUT_LD_FILE string default "src/mainboard/emulation/qemu-aarch64/memlayout.ld" diff --git a/src/mainboard/emulation/qemu-aarch64/mmio.c b/src/mainboard/emulation/qemu-aarch64/mmio.c index 0fac64d..a1dca5a 100644 --- a/src/mainboard/emulation/qemu-aarch64/mmio.c +++ b/src/mainboard/emulation/qemu-aarch64/mmio.c @@ -3,6 +3,8 @@ #include <console/uart.h> #include <mainboard/addressmap.h>
+uintptr_t io_port_mmio_base = 0x3eff0000; + uintptr_t uart_platform_base(unsigned int idx) { return VIRT_UART_BASE; diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index 5e46e68..45ba2f7 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -48,21 +48,11 @@ acpimmio_gpio0 = bar; }
-static uintptr_t io_bar; +uintptr_t io_port_mmio_base;
static void io_set_bar(void *bar) { - io_bar = (uintptr_t)bar; -} - -u8 io_read8(u16 reg) -{ - return read8p(io_bar + reg); -} - -void io_write8(u16 reg, u8 value) -{ - write8p(io_bar + reg, value); + io_port_mmio_base = (uintptr_t)bar; }
static void aoac_set_bar(void *bar) diff --git a/src/soc/amd/common/psp_verstage/include/arch/io.h b/src/soc/amd/common/psp_verstage/include/arch/io.h deleted file mode 100644 index efa128b..0000000 --- a/src/soc/amd/common/psp_verstage/include/arch/io.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ARCH_IO_H__ -#define __ARCH_IO_H__ - -#include <stdint.h> - -u8 io_read8(u16 reg); -void io_write8(u16 reg, u8 value); - -static inline void outb(uint8_t value, uint16_t port) -{ - io_write8(port, value); -} - -static inline uint8_t inb(uint16_t port) -{ - return io_read8(port); -} - -#endif