[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Expose UPD to disable Precision Time Management

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46856 )

Change subject: soc/intel/tigerlake: Expose UPD to disable Precision Time Management
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soc/intel/tigerlake: Expose UPD to disable Precision Time Management

Expose a config option that allows disabling the FSP UPD which controls
Precision Time Management for a particular PCIe root port.  Since this
is enabled by default the option is inverted to allow disabling for
a particular port while not affecting others.

BUG=b:160996445
TEST=boot on volteer with PTM disabled for the NVMe root port

Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46856/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f752b5f..fcd6b0c 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -242,6 +242,9 @@
    /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
    uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];

+	/* Disable PCIe Precision Time Measurement for Root Ports (enabled by default) */
+	uint8_t PciePtmDisable[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 887241b..1520cfe 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -186,6 +186,7 @@
    	params->PcieRpAdvancedErrorReporting[i] =
    		config->PcieRpAdvancedErrorReporting[i];
    	params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+		params->PciePtm[i] = !config->PciePtmDisable[i];
    }

/* Enable ClkReqDetect for enabled port */