Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39625 )
Change subject: soc/intel/xeon_sp: Modify FSP-T code caching parameters ......................................................................
soc/intel/xeon_sp: Modify FSP-T code caching parameters
With a hard-coded CBFS_SIZE can solve the booting issue on Tioga Pass, a more ideal way can be explored in the future.
Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/bootblock/bootblock.c 2 files changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/39625/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 94c0ac4..a9352275 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -122,5 +122,8 @@ hex default 0x80000
+config CBFS_SIZE + hex + default 0x1000000
endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 482f5b5..309a39c 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -30,8 +30,8 @@ .FsptCoreUpd = { .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, - .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, + .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), + .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE, .Reserved1 = {0}, }, .FsptConfig = {