Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48687 )
Change subject: volteer/variants/eldrid: Enable RTD3 for the NVMe device ......................................................................
volteer/variants/eldrid: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state.
BUG=b:161270810 TEST=tested on eldrid
Signed-off-by: Nick Chen nick_xr_chen@wistron.corp-partner.google.com Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/variants/eldrid/gpio.c M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 2 files changed, 9 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index e92f6b1..d2b08bc 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -24,7 +24,7 @@ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 1b86e0e..08d013e 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -175,6 +175,14 @@ device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A""