[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Enable TC Cold support

[John Zhao (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49244 )

Change subject: soc/intel/tigerlake: Enable TC Cold support
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49244/comment/b88f35a3_daaa8989 
PS3, Line 9: This change enables support for TC cold usb connect.
> Can you please add some information as to why this change is required?

Please go over https://chrome-internal-review.googlesource.com/c/chromeos/third_party/intel....
    if (TcssPeiConfig->IomConfig.DisableTccoldOnUsbConnected == 0) {
      //
      // CLEAR BIT 20 of IOM_TYPEC_SW_CONFIGURATION_1
      // 0 - Enable TC cold if only have USB2 or lower speed connected.
      //
      IomTypecConfigValue &= (~DISABLE_TCCOLD_ON_USB_CONNECTED);
    } else {
      //
      // SET BIT 20 of IOM_TYPEC_SW_CONFIGURATION_1
      // 1 - Disable TC cold when any USB2/3 device connected.
      //
      IomTypecConfigValue |= DISABLE_TCCOLD_ON_USB_CONNECTED;
    }

DisableTccoldOnUsbConnected=0 -> bit20 is NOT set (TCCold is not disabled)
DisableTccoldOnUsbConnected=1 -> bit21 is set (TCCold is disabled) which what we need to resolve the enumeration issue while plugging this usb3 into typec-to-a dongle.