Attention is currently required from: Mike Lee.
Hello Mike Lee,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/75381
to review the following change.
Change subject: mb/google/Screebo: Enable AUX DC biasing on C0 ......................................................................
mb/google/Screebo: Enable AUX DC biasing on C0
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.
BUG=b:283044004 BRANCH=none TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba Signed-off-by: mike mike5@huaqin.corp-partner.google.com --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/screebo/Makefile.inc M src/mainboard/google/rex/variants/screebo/overridetree.cb A src/mainboard/google/rex/variants/screebo/variant.c M src/soc/intel/meteorlake/gpio.c 6 files changed, 69 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75381/1
diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index a0dba44..4a6420c 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -10,6 +10,7 @@ #include <fw_config.h> #include <soc/ramstage.h> #include <stdlib.h> +#include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h>
WEAK_DEV_PTR(rp6_wwan); @@ -56,6 +57,16 @@ */ }
+void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + variant_update_soc_chip_config(config); +} + +void __weak variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + /* default implementation does nothing */ +} + static void mainboard_generate_s0ix_hook(void) { acpigen_write_if_lequal_op_int(ARG0_OP, 1); diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index 6bb52e2..58435f6 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -19,6 +19,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
const struct mb_cfg *variant_memory_params(void); +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); void variant_get_spd_info(struct mem_spd *spd_info); int variant_memory_sku(void); bool variant_is_half_populated(void); diff --git a/src/mainboard/google/rex/variants/screebo/Makefile.inc b/src/mainboard/google/rex/variants/screebo/Makefile.inc index 228886c..192041b 100644 --- a/src/mainboard/google/rex/variants/screebo/Makefile.inc +++ b/src/mainboard/google/rex/variants/screebo/Makefile.inc @@ -3,3 +3,4 @@ romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 2e7b208..9abe40c 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -1,3 +1,20 @@ +fw_config + field AUDIO 0 1 + option AUDIO_UNKNOWN 0 + option ALC1019_ALC5682I 1 + end + field DB_CONFIG 2 4 + option DB_UNKNOWN 0 + option DB_TYPEC 1 + option DB_TBT 2 + end + field MB_CONFIG 5 7 + option MB_UNKNOWN 0 + option MB_TYPEC 1 + option MB_TBT 2 + end +end + chip soc/intel/meteorlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c new file mode 100644 index 0000000..d42725b --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <fw_config.h> +#include <baseboard/variants.h> + +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + /*SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports. + * Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + * TcssAuxOri = 0101b + * Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + * Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + * motherboard to USBC connector + */ + if (fw_config_probe(FW_CONFIG(MB_CONFIG, MB_TYPEC))) { + config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_C16; + config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_C17; + config->tcss_aux_ori = 0x04; + } +} diff --git a/src/soc/intel/meteorlake/gpio.c b/src/soc/intel/meteorlake/gpio.c index 2662dde..2d6b65d 100644 --- a/src/soc/intel/meteorlake/gpio.c +++ b/src/soc/intel/meteorlake/gpio.c @@ -75,6 +75,7 @@ static const struct pad_community mtl_communities[] = { [COMM_0] = { /* GPP CPU, V, C */ .port = PID_GPIOCOM0, + .cpu_port = PID_GPIOCOM0, .first_pad = GPIO_COM0_START, .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,