Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )
Change subject: mainboard/google/volteer: Enable long cr50 ready pulses ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44359/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/chromeos.c:
https://review.coreboot.org/c/coreboot/+/44359/4/src/mainboard/google/voltee... PS4, Line 41: mainboard_silicon_init_params I would recommend moving this to mainboard_chip_init() in mainboard.c: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/th...
Basically add a helper function variant_update_devtree() and then use something like:
``` struct soc_intel_tigerlake_config *cfg = config_of_soc(); tlcl_lib_init(); if (cr50_supports_long_pulses()) cfg->LpmStateDisableMask = LPM_S0i3_4; ```
This ensures that the soc config gets updated by mainboard before SoC sets the FSP UPD.