Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35225 )
Change subject: soc/intel/common/block/cse: Move me_read_config32() to common code ......................................................................
Patch Set 21:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35225/19/src/soc/intel/common/block... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35225/19/src/soc/intel/common/block... PS19, Line 511: No CSE device
CSE device is disabled?
conveys the message
https://review.coreboot.org/c/coreboot/+/35225/19/src/soc/intel/common/block... File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/35225/19/src/soc/intel/common/block... PS19, Line 55: Configuration
PCI configuration space?
Done
https://review.coreboot.org/c/coreboot/+/35225/19/src/soc/intel/common/block... PS19, Line 68: /* HFSTS register offsets in PCI config space */ : enum { : PCI_ME_HFSTS1 = 0x40, : PCI_ME_HFSTS2 = 0x48, : PCI_ME_HFSTS3 = 0x60, : PCI_ME_HFSTS4 = 0x64, : PCI_ME_HFSTS5 = 0x68, : PCI_ME_HFSTS6 = 0x6C, : };
move before function declaration.
Done