Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33918 )
Change subject: src/mainboard/asus/am1i-a/buildOpts.c: uncomment the RAM speed-related defines ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/33918/1/src/mainboard/asus/am1i-a/buildOpts.... File src/mainboard/asus/am1i-a/buildOpts.c:
https://review.coreboot.org/#/c/33918/1/src/mainboard/asus/am1i-a/buildOpts.... PS1, Line 268: #define DDR400_FREQUENCY 200 ///< DDR 400 : #define DDR533_FREQUENCY 266 ///< DDR 533 : #define DDR667_FREQUENCY 333 ///< DDR 667 : #define DDR800_FREQUENCY 400 ///< DDR 800 : #define DDR1066_FREQUENCY 533 ///< DDR 1066 : #define DDR1333_FREQUENCY 667 ///< DDR 1333 : #define DDR1600_FREQUENCY 800 ///< DDR 1600 : #define DDR1866_FREQUENCY 933 ///< DDR 1866 : #define DDR2100_FREQUENCY 1050 ///< DDR 2100 : #define DDR2133_FREQUENCY 1066 ///< DDR 2133 : #define DDR2400_FREQUENCY 1200 ///< DDR 2400 : #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency : : /* QUANDRANK_TYPE*/ : #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM : #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM : : /* USER_MEMORY_TIMING_MODE */ : #define TIMING_MODE_AUTO 0 ///< Use best rate possible : #define TIMING_MODE_LIMITED 1 ///< Set user top limit : #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed : : /* POWER_DOWN_MODE */ : #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode : #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode :
see src/vendorcode/amd/agesa/f16kb/AGESA. […]
Okay, perhaps this commit is not needed then. Abandoning...