Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42236 )
Change subject: mb/google/volteer: Change PCH VR settings for better Sx power savings ......................................................................
mb/google/volteer: Change PCH VR settings for better Sx power savings
For Tigerlake platforms, this patch set optimized values for PCH external VR settings and ext rail voltage/current, to achieve better power savings in sleep states.
BUG=None BRANCH=None TEST=Build and boot volteer and check VR settings with debugger.
Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4
Signed-off-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.com Change-Id: Ief6194ec8109b6020056cb9e310a3b6519bc8424 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42236/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a55ef7d..fdf44fa 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -244,6 +244,29 @@ }, }"
+ register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_S0i1_S0i2 | + FIVR_ENABLE_S0i3 | + FIVR_ENABLE_S3 | + FIVR_ENABLE_S4 | + FIVR_ENABLE_S5, + .vnn_enable_bitmap = FIVR_ENABLE_S0i1_S0i2 | + FIVR_ENABLE_S0i3 | + FIVR_ENABLE_S3 | + FIVR_ENABLE_S4 | + FIVR_ENABLE_S5, + + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y