Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 44:
(4 comments)
Thanks for the review. Appreciate it!
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/fsp/FspmUpd.h:
PS42:
Ideally yes, however this is kind of a pre-release version. […]
In addition to FSP UPD header files,the FSP HOB header files are also moved to src/vendorcode/intel/fsp/fsp2_0. In the commit message, I stated that these header files are from a FSP engineering build.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpe.h:
PS42:
It seems that nothing in here is actually used, though the header is included by chip.h and uncore. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... PS42, Line 24: static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
Do the ranges mentioned in chapter 7. […]
PCH initialization is done by FSP, so we don't do anything here
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/spi.... File src/soc/intel/xeon_sp/spi.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/spi.... PS42, Line 26: case PCH_DEVFN_GSPI0: : return 1; : case PCH_DEVFN_GSPI1: : return 2;
Are these used for anything? I don't think we have them on LBG - we only have one SPI bus AFAICT.
Done