[coreboot-gerrit] Change in coreboot[master]: arch/x86: Add option for running romstage in DRAM

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32414 )

Change subject: arch/x86: Add option for running romstage in DRAM
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Patch Set 6:
> Patch Set 6:
>
> (2 comments)
> > You already have several TODOs left behind like bootblock-y += cache_as_ram.S
>
> Not in this patch.

CB:34477 CB:34478

I think the documentation should have made it more clear that verstage will be executing on the Security Processor, not the x86. If this implies it will not be possible to boot with custom verstage builds (due to the signing procedure on PSP binaries) please add such information in the documentation.

People may be restricted to the more traditional verstage between bootblock and romstage -approach because of this. You would then want the first stage as read-only, small, and not call any blobs. In other words, reset vector would go back into bootblock.