Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19496 )
Change subject: cpu/intel/pineview: Include speedstep ......................................................................
cpu/intel/pineview: Include speedstep
Needed to generate cpu entries.
Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/northbridge/intel/pineview/northbridge.c 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19496/1
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 082c472..dbf300b 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index b7fd8a1..ea55974 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -153,6 +153,7 @@ .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .acpi_fill_ssdt_generator = generate_cpu_entries, };
static void cpu_bus_init(device_t dev)