Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38682 )
Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38682/8//COMMIT_MSG@10 PS8, Line 10: and jsl in fsp params.
Won't the TGL FSP also support PCH-H? It seems the new numbers are […]
We do not have any mainboards added for PCH-H as of now. So we would like to support that on a need basis.
https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/38682/8/src/soc/intel/tigerlake/fsp... PS8, Line 108: for (i = 0; i < CONFIG_SOC_INTEL_USB2_PORT_MAX; i++) {
How about `ARRAY_SIZE(params->PortUsb20Enable)` instead? It's always better […]
Hello Nico. This is a valid point. But ARRAY_SIZE(params->PortUsb20Enable) would be 16 whereas JSL and TGL supports 8 and 10 USB2 ports respectively. With 16 as array size we would be running the for loop more than required. So the Kconfig way of defining the array size was to eliminate this and run the loop for required numbers for both JSL and TGL based on the no of usb ports they support. Please let me know your thoughts on this.