[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: move mainboard_silicon_init_params

[Shaunak Saha (Code Review)]

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44262 )

Change subject: soc/intel/tigerlake: move mainboard_silicon_init_params
......................................................................

soc/intel/tigerlake: move mainboard_silicon_init_params

This patch arranges mainboard_silicon_init_params before fetching
any config variables from devicetree. This would allow the variant
specific devicetree overrides to get consumed so that FSP UPD
parameters are initialized properly before SiliconInit.

BUG=b:158573805
TEST=Test that UPD values are set properly with variant specific
overrides of config's .

Signed-off-by: Shaunak Saha 
Change-Id: Idfce528efa7806e292071e092fb129b53a94a145
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44262/1

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index a61a025..5178d91 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -107,6 +107,8 @@
    if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
    	params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();

+	mainboard_silicon_init_params(params);
+
    /* D3Hot and D3Cold for TCSS */
    params->D3HotEnable = !config->TcssD3HotDisable;
    cpu_id = cpu_get_cpuid();
@@ -311,7 +313,6 @@

/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
    params->EnableMultiPhaseSiliconInit = 1;
-	mainboard_silicon_init_params(params);
 }

/*