Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29392 )
Change subject: src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ILB_BASE_SIZE ......................................................................
src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ILB_BASE_SIZE
The sizes of IO_BASE and ILB_BASE areas a incorrect. Correct IO_BASE_SIZE and ILB_BASE_SIZE values.
BUG=N/A TEST=Intel CherryHill CRB
Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4 Signed-off-by: Frans Hendriks fhendriks@eltan.com Reviewed-on: https://review.coreboot.org/c/29392 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/braswell/include/soc/iomap.h 1 file changed, 3 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h index c61983b..f49993e 100644 --- a/src/soc/intel/braswell/include/soc/iomap.h +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,7 +36,7 @@
/* IO Memory */ #define IO_BASE_ADDRESS 0xfed80000 -#define IO_BASE_SIZE 0x4000 +#define IO_BASE_SIZE 0x40000 #define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000 #define COMMUNITY_OFFSET_GPNORTH 0x08000 #define COMMUNITY_OFFSET_GPEAST 0x10000 @@ -43,7 +44,7 @@
/* Intel Legacy Block */ #define ILB_BASE_ADDRESS 0xfed08000 -#define ILB_BASE_SIZE 0x400 +#define ILB_BASE_SIZE 0x2000
/* SPI Bus */ #define SPI_BASE_ADDRESS 0xfed01000