[coreboot-gerrit] Change in ...coreboot[master]: soc/apollolake: Add UART0

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31864 )

Change subject: soc/apollolake: Add UART0
......................................................................

soc/apollolake: Add UART0

In my case, on UPsquared board with Celeron N3350 CPU,
I don't have UART2 but UART0.

Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31864
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/apollolake/uart.c
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
index a85ad1f..e8e2661 100644
--- a/src/soc/intel/apollolake/uart.c
+++ b/src/soc/intel/apollolake/uart.c
@@ -49,6 +49,13 @@
    },
 #else
    {
+		.console_index = 0,
+		.gpios = {
+			PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */
+			PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */
+		},
+	},
+	{
    	.console_index = 1,
    	.gpios = {
    		PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */