Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61352 )
Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ......................................................................
soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
Add L23 enter/exit, modPHY power gate, and source clock control methods. DL23: method for L2/L3 entry. L23D: method for L2/L3 exit. PSD0: method for modPHY power gate. SRCK: method for enabling/disable source clock. These optional methods are to be used in the device ACPI to construct flows with root port's power management functions.
Test: Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f --- M src/soc/intel/common/block/pcie/rtd3/chip.h M src/soc/intel/common/block/pcie/rtd3/rtd3.c 2 files changed, 62 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61352/1
diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h index 15b8f64..c2bad63 100644 --- a/src/soc/intel/common/block/pcie/rtd3/chip.h +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -45,6 +45,12 @@ * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. */ bool disable_l23; + + /* + * Provides L23, modPHY gating, source clock enabling methods to the device + * connected root port, mainly used in the device ACPI methods such as reset. + */ + bool ext_pm_support; };
#endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 9f91d21..a9df72a 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -100,6 +100,50 @@ acpigen_emit_namestring(RTD3_MUTEX_PATH); }
+/* Method to enter L2/L3 */ +static void +pcie_rtd3_acpi_method_dl23(void) +{ + acpigen_write_method_serialized("DL23", 0); + pcie_rtd3_acpi_l23_entry(); + acpigen_pop_len(); /* Method */ +} + +/* Method to exit L2/L3 */ +static void +pcie_rtd3_acpi_method_l23d(void) +{ + acpigen_write_method_serialized("L23D", 0); + pcie_rtd3_acpi_l23_exit(); + acpigen_pop_len(); /* Method */ +} + +/* Method to disable PCH modPHY power gating */ +static void +pcie_rtd3_acpi_method_pds0(unsigned int pcie_rp) +{ + acpigen_write_method_serialized("PSD0", 0); + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); + acpigen_pop_len(); /* Method */ +} + +/* Method to enable/disable the source clock */ +static void +pcie_rtd3_acpi_method_srck(unsigned int pcie_rp, + const struct soc_intel_common_block_pcie_rtd3_config *config) +{ + acpigen_write_method_serialized("SRCK", 1); + + if (config->srcclk_pin >= 0) { + acpigen_write_if_lequal_op_op(ARG0_OP, 0); + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); + acpigen_write_else(); + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); + acpigen_pop_len(); /* If */ + } + acpigen_pop_len(); /* Method */ +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, const struct soc_intel_common_block_pcie_rtd3_config *config, @@ -316,9 +360,20 @@ acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
+ if (config->ext_pm_support) { + pcie_rtd3_acpi_method_dl23(); + pcie_rtd3_acpi_method_l23d(); + } + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ - if (rp_type == PCIE_RP_PCH) + if (rp_type == PCIE_RP_PCH) { write_modphy_opregion(pcie_rp); + if (config->ext_pm_support) + pcie_rtd3_acpi_method_pds0(pcie_rp); + } + + if (config->ext_pm_support && config->srcclk_pin) + pcie_rtd3_acpi_method_srck(pcie_rp, config);
/* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states));