Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17109
-gerrit
commit a6930e3d0fed37d1ab7c012ea2d634fc1017c4e9 Author: Lin Huang hl@rock-chips.com Date: Thu Oct 20 14:22:11 2016 -0700
rockchip/rk3399: display: Do not allocate framebuffer in coreboot
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot.
CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible
Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang hl@rock-chips.com Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner jwerner@chromium.org Original-Reviewed-by: Julius Werner jwerner@chromium.org --- src/mainboard/google/gru/devicetree.cb | 1 - src/soc/rockchip/common/include/soc/vop.h | 3 ++- src/soc/rockchip/common/vop.c | 21 +++++++++++------- src/soc/rockchip/rk3288/display.c | 3 ++- src/soc/rockchip/rk3399/chip.h | 1 - src/soc/rockchip/rk3399/display.c | 28 +++++++++--------------- src/soc/rockchip/rk3399/include/soc/display.h | 3 +-- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3399/soc.c | 3 +-- 9 files changed, 29 insertions(+), 35 deletions(-)
diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index 7a421b2..6f177ed 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -15,7 +15,6 @@
chip soc/rockchip/rk3399 device cpu_cluster 0 on end - register "vop_id" = "0" register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "32" end diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h index f5ce431..98ad082 100644 --- a/src/soc/rockchip/common/include/soc/vop.h +++ b/src/soc/rockchip/common/include/soc/vop.h @@ -376,5 +376,6 @@ enum vop_modes { #define V_VASP(x) (((x)&0x1fff)<<16)
void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode); -void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid); +void rkvop_prepare(u32 vop_id, const struct edid *edid); +void rkvop_enable(u32 vop_id, u32 fbbase); #endif diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 668bee0..629072e 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -30,7 +30,19 @@ static struct rockchip_vop_regs * const vop_regs[] = { (struct rockchip_vop_regs *)VOP_LIT_BASE };
-void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) +void rkvop_enable(u32 vop_id, u32 fbbase) +{ + struct rockchip_vop_regs *preg = vop_regs[vop_id]; + + write32(&preg->win0_yrgb_mst, fbbase); + + /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only, + * but it's fine to write to it + */ + write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */ +} + +void rkvop_prepare(u32 vop_id, const struct edid *edid) { u32 lb_mode; u32 rgb_mode; @@ -85,13 +97,6 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); - - write32(&preg->win0_yrgb_mst, fbbase); - - /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only, - * but it's fine to write to it - */ - write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */ }
void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index f3dfac1..30c8ca1 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -108,7 +108,8 @@ void rk_display_init(device_t dev, u32 lcdbase, conf->framebuffer_bits_per_pixel, 0); rkvop_mode_set(conf->vop_id, &edid, detected_mode);
- rkvop_enable(conf->vop_id, lcdbase, &edid); + rkvop_prepare(conf->vop_id, &edid); + rkvop_enable(conf->vop_id, lcdbase);
switch (detected_mode) { case VOP_MODE_HDMI: diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h index 46baa8c..1f9462a 100644 --- a/src/soc/rockchip/rk3399/chip.h +++ b/src/soc/rockchip/rk3399/chip.h @@ -20,7 +20,6 @@ #include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */
struct soc_rockchip_rk3399_config { - u32 vop_id; gpio_t lcd_bl_pwm_gpio; gpio_t lcd_bl_en_gpio; u32 bl_power_on_udelay; diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 2679860..372e115 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -36,20 +36,14 @@
#include "chip.h"
-void rk_display_init(device_t dev, uintptr_t lcdbase, - unsigned long fb_size) +void rk_display_init(device_t dev) { struct edid edid; - uint32_t val; struct soc_rockchip_rk3399_config *conf = dev->chip_info; - uintptr_t lower = ALIGN_DOWN(lcdbase, MiB); - uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB); enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
- printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase)); - memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ - dcache_clean_invalidate_by_mva((void *)lower, upper - lower); - mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM); + /* let's use vop0 in rk3399 */ + uint32_t vop_id = 0;
switch (conf->vop_mode) { case VOP_MODE_NONE: @@ -58,12 +52,10 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, /* try EDP first, then HDMI */ case VOP_MODE_EDP: printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); - rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + rkclk_configure_vop_aclk(vop_id, 192 * MHz);
- /* select edp signal from vop0(big) or vop1(little) */ - val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) : - RK_CLRBITS(1 << 5); - write32(&rk3399_grf->soc_con20, val); + /* select edp signal from vop0 */ + write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
/* select edp clk from SoC internal 24M crystal, otherwise, * it will source from edp's 24M clock (that depends on @@ -89,7 +81,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, return; }
- if (rkclk_configure_vop_dclk(conf->vop_id, + if (rkclk_configure_vop_dclk(vop_id, edid.mode.pixel_clock * KHz)) { printk(BIOS_WARNING, "config vop err\n"); return; @@ -97,9 +89,9 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
edid_set_framebuffer_bits_per_pixel(&edid, conf->framebuffer_bits_per_pixel, 0); - rkvop_mode_set(conf->vop_id, &edid, detected_mode); + rkvop_mode_set(vop_id, &edid, detected_mode);
- rkvop_enable(conf->vop_id, lcdbase, &edid); + rkvop_prepare(vop_id, &edid);
switch (detected_mode) { case VOP_MODE_HDMI: @@ -115,5 +107,5 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, break; }
- set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + set_vbe_mode_info_valid(&edid, (uintptr_t)0); } diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h index 7ccde56..c10f1b9 100644 --- a/src/soc/rockchip/rk3399/include/soc/display.h +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -18,8 +18,7 @@
#define REF_CLK_24M (0x1 << 0)
-void rk_display_init(device_t dev, uintptr_t lcdbase, - unsigned long fb_size); +void rk_display_init(device_t dev); void mainboard_power_on_backlight(void);
#endif diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index a441281..f440dfb 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,7 +22,6 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10200000, 16M)
/* 8K of special SRAM in PMU power domain. */ SYMBOL(pmu_sram, 0xFF3B0000) diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 12c757f..e34ca09 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -39,8 +39,7 @@ static void soc_init(device_t dev) mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB));
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) - rk_display_init(dev, (uintptr_t)_framebuffer, - _framebuffer_size); + rk_display_init(dev); else printk(BIOS_INFO, "Display initialization disabled.\n");