Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58104 )
Change subject: mb/google/brya: Add PsysPmax setting to 145W ......................................................................
mb/google/brya: Add PsysPmax setting to 145W
This patch adds the setting of PsysPmax to 145W according to the brya board design.
BUG=b:195615830 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS
Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd Signed-off-by: Ryan Lin ryan.lin@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 41d1018..ad2399b 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -32,6 +32,8 @@ chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled"
+ register "PsysPmax" = "145" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.