Tim Wawrzynczak submitted this change.

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Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
mb/google/brya: Add PsysPmax setting to 145W

This patch adds the setting of PsysPmax to 145W according to
the brya board design.

BUG=b:195615830
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS

Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 41d1018..ad2399b 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -32,6 +32,8 @@
chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"

+ register "PsysPmax" = "145"
+
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port

register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port

1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
Gerrit-Change-Number: 58104
Gerrit-PatchSet: 3
Gerrit-Owner: Ryan Lin <ryan.lin@intel.com>
Gerrit-Reviewer: Hou-hsun Lee <hou-hsun.lee@intel.com>
Gerrit-Reviewer: Kane Chen <kane.chen@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged