[coreboot-gerrit] Change in coreboot[master]: tigerlake: enable DPTF functionality for volteer

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41427 )

Change subject: tigerlake: enable DPTF functionality for volteer
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/41427/2/src/mainboard/google/voltee... 
File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/41427/2/src/mainboard/google/voltee... 
PS2, Line 167: 	register "power_limits_config" = "{
             : 		.tdp_pl1_override = 15,
             : 		.tdp_pl2_override = 60,
             : 	}"
> This is the baseboard, and just be the default for all volteer boards unless they explicitly overrid […]

even on volteer, we're building with 2 core and 4 core CPUs.
intel specifies lower PLx values for the 2 core SKU vs the
4 core SKU. i'm OK with this if there's a another patch
in the series to tune these based on run-time CPU specs.