[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51159 )

Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
......................................................................

soc/intel/common/block/irq: Add support for intel_write_pci0_PRT

Add a new function to fill out the data structures necessary to generate
a _PRT table.

Signed-off-by: Tim Wawrzynczak 
Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62
---
M src/soc/intel/common/block/include/intelblocks/irq.h
M src/soc/intel/common/block/irq/irq.c
2 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/51159/1

diff --git a/src/soc/intel/common/block/include/intelblocks/irq.h b/src/soc/intel/common/block/include/intelblocks/irq.h
index 8548f1e..d41fcf4 100644
--- a/src/soc/intel/common/block/include/intelblocks/irq.h
+++ b/src/soc/intel/common/block/include/intelblocks/irq.h
@@ -37,5 +37,7 @@

const struct pci_irq_entry *assign_pci_irqs(size_t *num);
 const struct soc_irq_constraints *soc_irq_constraints(void);
+size_t generate_pin_irq_map(struct slot_pin_irq_map pin_irq_map[32][4],
+			    struct pirq_map *pirq_map);

#endif /* SOC_INTEL_COMMON_IRQ_H */
diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c
index cb004aa..62fbb12 100644
--- a/src/soc/intel/common/block/irq/irq.c
+++ b/src/soc/intel/common/block/irq/irq.c
@@ -5,6 +5,7 @@
 #include <device/pci.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/irq.h>
+#include <intelblocks/lpc_lib.h>
 #include <soc/irq.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <string.h>
@@ -366,3 +367,34 @@

return count;
 }
+
+size_t generate_pin_irq_map(struct slot_pin_irq_map pin_irq_map[32][4],
+			    struct pirq_map *pirq_map)
+{
+	const uint8_t *legacy_pirq_routing;
+	size_t num_devs = 0;
+	size_t pirq_routes;
+	size_t i;
+
+	memset(pin_irq_map, 0, sizeof(struct slot_pin_irq_map[32][4]));
+	memset(pirq_map, 0, sizeof(*pirq_map));
+
+	pirq_map->type = PIRQ_GSI;
+	legacy_pirq_routing = lpc_get_pch_pirq_routing(&pirq_routes);
+	for (i = 0; i < MAX_PIRQS && i < pirq_routes; i++)
+		pirq_map->gsi[i] = legacy_pirq_routing[i];
+
+	for (i = 0; i < entry_count; i++) {
+		unsigned int slot = PCI_SLOT(entries[i].devfn);
+		unsigned int pin_idx = entries[i].pin - PCI_INT_A;
+		if (!pin_irq_map[slot][pin_idx].gsi && !pin_irq_map[slot][pin_idx].pirq) {
+			pin_irq_map[slot][pin_idx].gsi = entries[i].irq;
+
+			/* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */
+			pin_irq_map[slot][pin_idx].pirq = (enum pirq)entries[i].pin;
+			++num_devs;
+		}
+	}
+
+	return num_devs;
+}