[coreboot-gerrit] Change in coreboot[master]: soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm

[Michael Niewöhner (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Angel Pons, Arthur Heymans, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Paul Menzel, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Srinidhi N Kaushik, Lean Sheng Tan, V Sowmya, Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35902

to look at the new patch set (#9).

Change subject: soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm
......................................................................

soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm

This change reworks the PRMRR size selection and implements an algorithm
for PRMRR size selection which will be needed in a follow-up change to
make the maximum PRMRR size user-selectable via Kconfig.

Currently, PRMRR size must be set in the devicetree, while the value has
to be verified to be working with the CPU. The selection of a valid
PRMRR size is now done by an algorithm that tries to find a supported
PRMRR size within a possibly specified limit by looking at
MSR_PRMRR_VALID_CONFIG and trying to select the highest possible value
at runtime within a possibly specified limit.

That (hopefully) prevents setting a wrong, unsupported static value.

The limit can be set via the devicetree setting PrmrrSize, that will be
replaced by Kconfig in the follow-up change. When a too strict limit is
set, coreboot will die, printing an error message.

Further, this change does some restructuring of memmap.c (for the listed
platforms) to a) integrate the previously described functionality and b)
to align common functionality for later move to the common section.

Before this reunification can happen, some more details about PRMRR, its
influence on SGX-enabled and -disabled systems have to be investigated
and understood. This is being worked on.

Todo: needs testing

Signed-off-by: Michael Niewöhner 
Change-Id: I8a773362f8d09c8a33ff0dfac357edc6ea3564e0
---
M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/soc/intel/apollolake/chip.h
A src/soc/intel/apollolake/include/soc/memmap.h
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/cannonlake/chip.h
A src/soc/intel/cannonlake/include/soc/memmap.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/icelake/chip.h
A src/soc/intel/icelake/include/soc/memmap.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/romstage/fsp_params.c
M src/soc/intel/skylake/chip.h
A src/soc/intel/skylake/include/soc/memmap.h
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
24 files changed, 241 insertions(+), 91 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35902/9