[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
PS5, Line 177: 	enable_ramstage_caching(top_of_ram, top_of_ram_size);
> Also refer to this https://github. […]

NEM enhance or CQOS is special because it treated data and code cache differently than whats been done in NEM mode, but that doesn't mean that NEM enhance and CQOS provides more cache size than actually its available. CPU cache sizes are fixed in both cases

I could see the same benefit with very old SKL code when we don't have NEM enhanced implemented