Maciej Matuszczyk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35863 )
Change subject: mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board of T60 ......................................................................
mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board of T60
Add ThinkPad R60 support, only tested on unit with Intel GPU, now as variant board of ThinkPad T60.
- It can be 100 % Open Source. - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't why it appears like that. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Might be fact that my unit is missing one of power line filtering capacitors.
Image of issue with the screen: [1] https://imgur.com/a/0wpMGsm
Change-Id: I1eb0b2647beeb21362d494b106c6c6a3c5fafa9e Signed-off-by: Maciej Matuszczuk maccraft123mc@gmail.com --- M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/t60/Kconfig.name M src/mainboard/lenovo/t60/board_info.txt A src/mainboard/lenovo/t60/variants/r60/board_info.txt A src/mainboard/lenovo/t60/variants/r60/gpio.c A src/mainboard/lenovo/t60/variants/t60/board_info.txt A src/mainboard/lenovo/t60/variants/t60/gpio.c 7 files changed, 368 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35863/1
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index e4e87c9..81c2e1f 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T60 +if BOARD_LENOVO_T60 || BOARD_LENOVO_R60
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,13 +24,23 @@ select I945_LVDS select INTEL_GMA_HAVE_VBT
+config VARIANT_DIR + string + default "t60" if BOARD_LENOVO_T60 + default "r60" if BOARD_LENOVO_R60 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_DIR string default lenovo/t60
config MAINBOARD_PART_NUMBER string - default "ThinkPad T60" + default "ThinkPad T60" if BOARD_LENOVO_T60 + default "ThinkPad R60" if BOARD_LENOVO_R60
config MAX_CPUS int diff --git a/src/mainboard/lenovo/t60/Kconfig.name b/src/mainboard/lenovo/t60/Kconfig.name index f02fc3d..408c693 100644 --- a/src/mainboard/lenovo/t60/Kconfig.name +++ b/src/mainboard/lenovo/t60/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" + +config BOARD_LENOVO_R60 + bool "ThinkPad R60" diff --git a/src/mainboard/lenovo/t60/board_info.txt b/src/mainboard/lenovo/t60/board_info.txt index 59ec88c..0318ee4 100644 --- a/src/mainboard/lenovo/t60/board_info.txt +++ b/src/mainboard/lenovo/t60/board_info.txt @@ -1,4 +1,5 @@ -Board name: T60/T60p +Vendor name: Lenovo +Board name: T60/T60p/R60 baseboard Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t60/variants/r60/board_info.txt b/src/mainboard/lenovo/t60/variants/r60/board_info.txt new file mode 100644 index 0000000..59ec88c --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/r60/board_info.txt @@ -0,0 +1,7 @@ +Board name: T60/T60p +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/t60/variants/r60/gpio.c b/src/mainboard/lenovo/t60/variants/r60/gpio.c new file mode 100644 index 0000000..f220b2b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/r60/gpio.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ + .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ + .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ + .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ + .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ + .gpio19 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ + .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio19 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ + .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ + .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ + .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ + .gpio48 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio48 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/t60/variants/t60/board_info.txt b/src/mainboard/lenovo/t60/variants/t60/board_info.txt new file mode 100644 index 0000000..b34244b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/board_info.txt @@ -0,0 +1,7 @@ +Board name: R60 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/t60/variants/t60/gpio.c b/src/mainboard/lenovo/t60/variants/t60/gpio.c new file mode 100644 index 0000000..1f527b7 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/gpio.c @@ -0,0 +1,225 @@ +/* + + * This file is part of the coreboot project. + + * + + * Copyright (C) 2019 Maciej Matuszczyk maccraft123mc@gmail.com. + + * + + * This program is free software; you can redistribute it and/or modify + + * it under the terms of the GNU General Public License as published by + + * the Free Software Foundation; version 2 of the License. + + * + + * This program is distributed in the hope that it will be useful, + + * but WITHOUT ANY WARRANTY; without even the implied warranty of + + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + * GNU General Public License for more details. + + */ + + +#include <southbridge/intel/common/gpio.h> + + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + + .gpio1 = GPIO_MODE_GPIO, /* HDD_DTCT */ + + .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ + + .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ + + .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ + + .gpio9 = GPIO_MODE_GPIO, + + .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ + + .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ + + .gpio13 = GPIO_MODE_GPIO, + + .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ + + .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ + + .gpio19 = GPIO_MODE_GPIO, /* GBE_RST# */ + + .gpio21 = GPIO_MODE_GPIO, /* LCD_PRESENCE */ + + .gpio22 = GPIO_MODE_GPIO, /* FWH_WP */ + + .gpio24 = GPIO_MODE_GPIO, + + .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ + + .gpio26 = GPIO_MODE_GPIO, + + .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ + + .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ + +}; + + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + + .gpio1 = GPIO_DIR_INPUT, + + .gpio6 = GPIO_DIR_INPUT, + + .gpio7 = GPIO_DIR_INPUT, + + .gpio8 = GPIO_DIR_INPUT, + + .gpio9 = GPIO_DIR_INPUT, + + .gpio10 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_INPUT, + + .gpio13 = GPIO_DIR_INPUT, + + .gpio14 = GPIO_DIR_INPUT, + + .gpio15 = GPIO_DIR_INPUT, + + .gpio19 = GPIO_DIR_OUTPUT, + + .gpio21 = GPIO_DIR_INPUT, + + .gpio22 = GPIO_DIR_OUTPUT, + + .gpio24 = GPIO_DIR_OUTPUT, + + .gpio25 = GPIO_DIR_OUTPUT, + + .gpio26 = GPIO_DIR_OUTPUT, + + .gpio27 = GPIO_DIR_OUTPUT, + + .gpio28 = GPIO_DIR_OUTPUT, + +}; + + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + + .gpio19 = GPIO_LEVEL_HIGH, + + .gpio24 = GPIO_LEVEL_HIGH, + + .gpio25 = GPIO_LEVEL_HIGH, + + .gpio26 = GPIO_LEVEL_LOW, + + .gpio27 = GPIO_LEVEL_HIGH, + + .gpio28 = GPIO_LEVEL_HIGH, + +}; + + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + + .gpio1 = GPIO_INVERT, + + .gpio6 = GPIO_INVERT, + + .gpio7 = GPIO_INVERT, + + .gpio8 = GPIO_INVERT, + + .gpio12 = GPIO_INVERT, + + .gpio13 = GPIO_INVERT, + +}; + + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + +}; + + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + + .gpio34 = GPIO_MODE_GPIO, /* SMB_3B_EN */ + + .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ + + .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ + + .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ + + .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ + + .gpio48 = GPIO_MODE_GPIO, /* FWH_TBL */ + + +}; + + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + + .gpio34 = GPIO_DIR_INPUT, + + .gpio36 = GPIO_DIR_INPUT, + + .gpio37 = GPIO_DIR_INPUT, + + .gpio38 = GPIO_DIR_INPUT, + + .gpio39 = GPIO_DIR_INPUT, + + .gpio48 = GPIO_DIR_OUTPUT, + + +}; + + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + + .gpio33 = GPIO_LEVEL_LOW, + + .gpio35 = GPIO_LEVEL_HIGH, + + .gpio48 = GPIO_LEVEL_HIGH, + +}; + + +const struct pch_gpio_map mainboard_gpio_map = { + + .set1 = { + + .mode = &pch_gpio_set1_mode, + + .direction = &pch_gpio_set1_direction, + + .level = &pch_gpio_set1_level, + + .invert = &pch_gpio_set1_invert, + + }, + + .set2 = { + + .mode = &pch_gpio_set2_mode, + + .direction = &pch_gpio_set2_direction, + + .level = &pch_gpio_set2_level, + + }, + +};