[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63691 )

Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................

soc/intel/alderlake: Implement PMC feature lock

This patch locks PMC features like: debug mode configuration and host
read access to PMC XRAM.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik 
Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c
---
M src/soc/intel/alderlake/include/soc/pmc.h
M src/soc/intel/alderlake/lockdown.c
2 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63691/1

diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h
index ca11ae9..07206cb 100644
--- a/src/soc/intel/alderlake/include/soc/pmc.h
+++ b/src/soc/intel/alderlake/include/soc/pmc.h
@@ -76,6 +76,10 @@

#define PRSTS				0x1810

+#define PM_CFG				0x1818
+#define    PM_CFG_DBG_MODE_LOCK	(1 << 27)
+#define    PM_CFG_XRAM_READ_DISABLE	(1 << 22)
+
 #define S3_PWRGATE_POL			0x1828
 #define    S3DC_GATE_SUS		(1 << 1)
 #define    S3AC_GATE_SUS		(1 << 0)
diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c
index 3e05b0d..4ee223e 100644
--- a/src/soc/intel/alderlake/lockdown.c
+++ b/src/soc/intel/alderlake/lockdown.c
@@ -74,6 +74,17 @@
    return;
 }

+/*
+ * This function to lock PMC features like:
+ * debug mode configuration and host read access to PMC XRAM.
+ */
+static void pmc_feature_lock(void)
+{
+	void *pmcbase = pmc_mmio_regs();
+
+	setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | PM_CFG_XRAM_READ_DISABLE);
+}
+
 static void pmc_lockdown_cfg(int chipset_lockdown)
 {
    /* PMSYNC */
@@ -87,6 +98,7 @@
    if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
    	pmc_st_pg_lock();
    	pmc_soft_strap_interface_lock();
+		pmc_feature_lock();
    }
 }