Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3824
-gerrit
commit 5fc6ca6a88c20b9e5a21a9faa7612a99229c329b Author: Siyuan Wang wangsiyuanbuaa@gmail.com Date: Tue Jul 9 17:32:42 2013 +0800
amd/agesa/hudson/early_setup.c: Move enabling of Super I/O ports to southbridge
Currently enabling of the standard ports to configure the Super I/O is done in each mainboard’s (not Parmer) `romstage.c` file.
Move this into the function `hudson_lpc_port80()` in `early_setup.c` as it is a southbridge feature.
This change is split out from patch set [1].
[1] http://review.coreboot.org/#/c/3783/2
Change-Id: Iad37ce85f42a1870dc3db425dbe0e24408824f95 Signed-off-by: Siyuan Wang SiYuan.Wang@amd.com Signed-off-by: Siyuan Wang wangsiyuanbuaa@gmail.com Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/mainboard/amd/thatcher/romstage.c | 5 ----- src/mainboard/asus/f2a85-m/romstage.c | 6 ------ src/southbridge/amd/agesa/hudson/early_setup.c | 3 +++ 3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 601aa7e..18ca767 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -55,11 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80(); //__asm__ volatile ("1: jmp 1b"); - /* TODO: */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte);
if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 5773eba..8c3d6b6 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -74,12 +74,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
- /* enable SIO decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - post_code(0x30);
/* enable SB MMIO space */ diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..af5bcbd 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -46,6 +46,9 @@ void hudson_lpc_port80(void) byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */ + pci_write_config8(dev, 0x48, byte); }
int s3_save_nvram_early(u32 dword, int size, int nvram_pos)