[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable MrcSafeConfig

[Dossym Nurmukhanov (Code Review)]

Dossym Nurmukhanov has uploaded a new patch set (#3) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/40106 )

Change subject: soc/intel/tigerlake: Disable MrcSafeConfig
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soc/intel/tigerlake: Disable MrcSafeConfig

This change disables MrcSafeConfig option during MRC training.
MrcSafeConfig was enabled as part of the early testing.
Now with FSP 2527, there is no need to set this config anymore.

BUG=b:150357377
BRANCH=master
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
---
M src/soc/intel/tigerlake/meminit.c
1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/40106/3