[coreboot-gerrit] Change in coreboot[master]: amd/agesa: Make BottomIo position configurable

[Mike Banon (Code Review)]

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38472 )

Change subject: amd/agesa: Make BottomIo position configurable
......................................................................

amd/agesa: Make BottomIo position configurable

Some PCI peripherals, such as discrete VGA adapters, require a great
amount of memory mapped IO. This patch allows the user to select at
build time the bottom IO to leave enough space for such devices.

We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated. 0x40000000 has been successfully
boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb).

Signed-off-by: Mike Banon 
Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0
---
M src/northbridge/amd/agesa/Kconfig
M src/northbridge/amd/agesa/family14/state_machine.c
M src/northbridge/amd/agesa/family15tn/state_machine.c
M src/northbridge/amd/agesa/family16kb/state_machine.c
4 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38472/1

diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index e1e129a..346e2c3 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -20,6 +20,18 @@

if NORTHBRIDGE_AMD_AGESA

+config BOTTOMIO_POSITION
+	hex "Bottom of 32-bit IO space"
+	default 0x40000000
+	help
+	  If PCI peripherals with big BARs are connected to the system
+	  the bottom of the IO must be decreased to allocate such
+	  devices.
+
+	  Declare the beginning of the 128MB-aligned MMIO region.  This
+	  option is useful when PCI peripherals requesting large address
+	  ranges are present.
+
 config CONSOLE_VGA_MULTI
    bool
    default n
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index b49dac0..345f36a 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -60,6 +60,7 @@

void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
 {
+	Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24);
 }

void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c
index dafb64c..092c781 100644
--- a/src/northbridge/amd/agesa/family15tn/state_machine.c
+++ b/src/northbridge/amd/agesa/family15tn/state_machine.c
@@ -30,6 +30,7 @@

void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
 {
+	Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24);
 }

void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c
index 7794f2d..0ffa5d5 100644
--- a/src/northbridge/amd/agesa/family16kb/state_machine.c
+++ b/src/northbridge/amd/agesa/family16kb/state_machine.c
@@ -32,6 +32,8 @@
 {
    AGESA_STATUS status;

+	Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24);
+
    if (CONFIG(ENABLE_MRC_CACHE)) {
    	status = OemInitResume(&Post->MemConfig.MemContext);
    	if (status == AGESA_SUCCESS)