[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB

[Kevin Chang (Code Review)]

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51200 )

Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
......................................................................

mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB

Disable SA GV in EVT MB, because some MB is using wrong Samsung date code memory.

BUG=b:179747696
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang 
Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f
---
M src/mainboard/google/volteer/romstage.c
M src/mainboard/google/volteer/variants/lindar/memory.c
M src/soc/intel/tigerlake/include/soc/romstage.h
3 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/51200/1

diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c
index f3fb454..dadaccc 100644
--- a/src/mainboard/google/volteer/romstage.c
+++ b/src/mainboard/google/volteer/romstage.c
@@ -22,4 +22,5 @@
    bool half_populated = gpio_get(GPIO_MEM_CH_SEL);

memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated);
+	memcfg_variant_init(mupd);
 }
diff --git a/src/mainboard/google/volteer/variants/lindar/memory.c b/src/mainboard/google/volteer/variants/lindar/memory.c
index f9350d1..52a0061 100644
--- a/src/mainboard/google/volteer/variants/lindar/memory.c
+++ b/src/mainboard/google/volteer/variants/lindar/memory.c
@@ -1,6 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <baseboard/variants.h>
+#include <memory_info.h>
+#include <fw_config.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/romstage.h>

static const struct mb_cfg board_memcfg = {
    .type = MEM_TYPE_LP4X,
@@ -59,3 +63,13 @@
 {
    return &board_memcfg;
 }
+
+void __weak memcfg_variant_init(FSPM_UPD *mupd)
+{
+	uint32_t board_version;
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
+	if (google_chromeec_get_board_version(&board_version) == 0
+		&& board_version == 1)
+	mem_cfg->SaGv = 0x00;
+}
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h
index ba44f2d..3c7c545 100644
--- a/src/soc/intel/tigerlake/include/soc/romstage.h
+++ b/src/soc/intel/tigerlake/include/soc/romstage.h
@@ -7,6 +7,7 @@

void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
+void __weak memcfg_variant_init(FSPM_UPD *mupd);

/* Board type */
 enum board_type {