Alexander Couzens (lynxis@fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8294
-gerrit
commit c30b34e4fffc1b3f5107006a8d3ab0c1c038eb4e Author: Alexander Couzens lynxis@fe80.eu Date: Wed Jan 28 01:51:04 2015 +0100
cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize(). Most of these aren't documented in public MSRs.
Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547 Signed-off-by: Alexander Couzens lynxis@fe80.eu --- src/cpu/intel/fsp_model_206ax/finalize.c | 5 +++++ src/cpu/intel/haswell/finalize.c | 5 +++++ src/cpu/intel/model_2065x/finalize.c | 6 +++++- src/cpu/intel/model_206ax/finalize.c | 5 +++++ 4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 4ed5d1e..179d978 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -43,6 +43,8 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_model_206ax_finalize_smm(void) { + /* Look into Bios Writer's Guide for the meaning of these MSR */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ @@ -67,6 +69,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif
+ /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1731322..0a53a25 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -46,6 +46,8 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_cpu_haswell_finalize_smm(void) { #if 0 + /* Look into Bios Writer's Guide for the meaning of these MSR */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ @@ -70,7 +72,10 @@ void intel_cpu_haswell_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif
+ /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); #endif } diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index b37a84c..3c494e4 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -44,6 +44,8 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_model_2065x_finalize_smm(void) { + /* Look into Bios Writer's Guide for the meaning of these MSRs */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ @@ -67,7 +69,9 @@ void intel_model_2065x_finalize_smm(void) msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 2c215a4..6d16c95 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -44,6 +44,8 @@ static void msr_set_bit(unsigned reg, unsigned bit)
void intel_model_206ax_finalize_smm(void) { + /* Look into Bios Writer's Guide for the meaning of these MSR */ + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */ @@ -68,6 +70,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif
+ /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); }