Hello build bot (Jenkins), Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48738
to look at the new patch set (#5).
Change subject: soc/intel/xeon_sp/cpx: Disable isoch operation for performance ......................................................................
soc/intel/xeon_sp/cpx: Disable isoch operation for performance
Isochronous operation negatively impacts memory performance, as per Intel MLC (Memory Latency Checker) benchmark results. Thus, disable isochronous operation, like analogous UEFI firmware does. The MLC results after disabling isoch:
"--max_bandwidth" ALL Reads : 106948.17 3:1 Reads-Writes : 101580.46 2:1 Reads-Writes : 100523.26 1:1 Reads-Writes : 99059.44 Stream-triad like : 97762.47
"--peak_injection_bandwidth" ALL Reads : 105724.3 3:1 Reads-Writes : 100655.8 2:1 Reads-Writes : 99463 1:1 Reads-Writes : 98708 Stream-triad like : 91515
The MLC results before disabling isoch:
"--max_bandwidth" ALL Reads : 88824.96 3:1 Reads-Writes : 94820.81 2:1 Reads-Writes : 94867.53 1:1 Reads-Writes : 92567.36 Stream-triad like : 91900.43
"--peak_injection_bandwidth" ALL Reads : 88859.6 3:1 Reads-Writes : 94064 2:1 Reads-Writes : 94186.2 1:1 Reads-Writes : 92516.1 Stream-triad like : 85147.4
TEST=On OCP Delta Lake, verify that MLC benchmark results have improved.
Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- M src/soc/intel/xeon_sp/cpx/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48738/5